CK803S is a low-cost embedded CPU core delivered to the field of microcontrollers by its low cost, low power and high performance.CK803S implements most of the CSKY V2 instructions, DSP acceleration instructions and single-precision floating point instructions. Furthermore, CK803S adopts a low cost 3-stage pipeline and user-extensible storage architecture. CK803S family includes basic core (CK803S), electromechanical and audio enhancement (CK803SE), floating point extension (CK803SF), and trusted execution extension (CK803ST).
Main technical features of CK803S
· Reduced instruction set architecture, 32-bit data, 16/32-bit variable length instructions;
· Performance: 1.5DMIPS/MHz;
· 3-stage pipeline, single issue in-order execution;
· Static branch prediction;
· One-cycle execution delay of most instructions;
· Back-to-back LD/ST data access;
· 3 bus interfaces including instruction bus, data bus and system bus. Instruction bus/data bus adopt AHB-Lite protocol, while system bus adopting AHB or AHB-Lite protocol;
· Multi-mode dynamic power management;
· 13 cycles interrupt latency from interrupt asserting to interrupt handler processing;
· Memory access protection, 0~8 memory protection regions;
· Tightly-coupled system IP, including vector interrupt controller, timer and power management unit;
· Supports single-precision floating point arithmetic;
· Supports DSP arithmetic acceleration;
· Trusted execution technology against software attack;
· Configurable cache;
· Configurable hardware debugger supporting on-chip hardware debugging;
Main technical parameters of CK803S
Application fields of CK803S
· Automotive electronics
· Industrial control
· Wireless network and various portable applications
Structural and design features of CK803S
CK803S implements high efficient and low cost micro architecture. The minimum core area of CK803S is 25,000 gates. CK803S adopts a simplified 3-stage pipeline including fetch, decode and execute. The fetch stage implements a low-cost static branch predictor to achieve prediction accuracy up to 80%. The decode stage takes responsible for the access phase of loads and stores and the execute stage takes responsible for the data phase. The rest of instructions are executed and written back in execute stage. CK803s has developed DSP instruction subset to support audio and electromechanical acceleration, and a low-cost floating point unit to support single-precision floating point arithmetic.
CK803S adopts Harvard architecture, and a local instruction bus and data bus are implemented. These local buses are connected to system bus, instruction bus and data bus through bus matrix unit. It supports a configurable memory protection unit (MPU) to protect data access to memory system.
CK803S supports multi-mode low power design technology, and provides software different layer of low power to choose. Fine-grained clock gating is adopted to eliminate dynamic power consumption in low power mode.
Trusted execution technology for IOT security
For IOT security, CK803S has developed the trusted execution technology based on virtualized trusted world and non-trusted world, which protects secure data in trusted world, and offers multiple layers of trusted protection features including trusted interrupt response and trusted debugging.