CK810 is a high-performance CPU core delivered for high-end embedded applications. Based on C-SKY V2 architecture and an optimized microarchitecture, it achieves industry-leading performance. CK810 implements 16/32-bit variable length instruction system as a basic, and enhances with high-performance vector DSP instruction subset and floating point instruction subset. CK810 adopts advanced 8-stage, dual-issue superscalar pipeline and out-of-order speculative execution framework to achieve high frequency, high performance and power efficiency. CK810series processors include basic core (CK810), floating point enhancement (CK810F), multimedia enhancement (CK810D), and multiple-processing extension (CK810MP).
Main technical features of CK810
· Reduced instruction set computer architecture, 32-bit data, 16/32-bit variable length instruction;
· Performance: 2.5DMIPS/MHz;
· 8-stagedual-issue superscalar pipeline;
· Out-of-order issue, out-of-order execution and in-order retirement of instructions;
· Hybrid branch prediction technology supporting branch direction prediction, return address prediction and indirect jump address prediction;
· Low-latency data forwarding technology, low-cost register renaming technology;
· Out-of-order speculative execution framework and distributed instruction issue queue;
· Non-blocking data cache, out-of-order load/store unit;
· Memory copy acceleration technology;
· On-chip MMU, automatic hardware refilling of page-table entry;
· On-chip instruction cache and data cache;
· AXI system bus interface or AXI/AHB dual-bus interface with configurable data width;
· Supports single precision and double precision data types;
· Supports vector DSP processing with 128-bit data width;
· Hardware debugger supporting on-chip hardware debugging;
Main technical parameters of CK810
Application fields of CK810
· Next-generation HDTV and STB (set top box);
· Intelligent monitoring;
· Vehicle navigation;
· Intelligent mobile terminal;
Structural and design features of CK810
CK810adopts advanced microarchitecture for high-performance computing. It realizes 8-stage pipeline. Fetch unit integrates bimode branch predictor, branch target buffer and return address stack. Issue unit is designed with 3dedicated instruction queues for two ALU pipelines and one Load/store pipeline. Load/store unit is capable of handling loads and stores issued out-of-order.CK810 supports multiple outstanding transactions to improve memory access performance.
CK810 supports Harvard memory architecture. Single-AXI-bus interface or AXI/AHB dual-bus interface is configurable for users. Multi-beat outstanding access is supported to improve the bus bandwidth. CK810 also supports the management of memory address and realizes the mapping of virtual address to physical address via hardware TLB. Finally, CK810 supports various low-power operating modes and fine-grained clock gating logic.
CK810 supports multi-core designs to further scale performance increase. CK810MP supports collaborative working of 1~4 cores with SCU (snoop control unit) to realize cache coherence. CK810MP also supports different multi-processing architectures including symmetric multi-processing (SMP) and asymmetric multi-processing (AMP). CK810MP fully supports mainstream SMP operating systems.
Vector arithmetic extension units of CK810
CK810implements configurable vector computing engine to support floating point arithmetic and vector DSP arithmetic. Vector computing engine contains sixteen (16) 128-bit vector purpose registers and supports the element size of byte/half-word/word. Vector computing engine also includes floating point unit which supports single-precision, double-precision and SIMD processing. Vector DSP unit is designed with 84 instructions and can realize the acceleration of typical audio &video key algorithms including DCT/DWT/FFT/motion estimation/motion compensation and so on.