CK807 is a high efficiency CPU core delivered for medium / high-end embedded applications. Based on C-SKY V2 instruction set architecture and 16/32-bit variable length instruction, CK807 implements single-precision and double-precision floating-point instructions to perform an outstanding performance and energy efficiency. CK807makes use of an advanced 8-stage superscalar pipeline enhanced with instruction / data cache access filter and loop program execution for a perfect balance between performance and power consumption. CK807series processors include basic core(CK807), floating-point enhancement(CK807F)and multiple-processing extension (CK807MP).
Main technical features of CK807
· Reduced instruction set computer architecture, 32-bit data, 16/32-bit variable length instruction;
· Performance: 2.0DMIPS/MHz;
· 8-stagedual-issue pipeline;
· Out-of-order issue, out-of-order execution and in-order retirement;
· Hybrid branch prediction technology supporting branch direction prediction, return address prediction and indirect jump address prediction;
· Reservation stations based out-of-order speculative execution mechanism;
· Non-blocking data cache;
· Low-power execution technology for loop programs;
· Low-power access filtering technology for instruction/data cache;
· On-chip MMU, automatic hardware refilling of page-table entry;
· On-chip instruction cache and data cache;
· AXI system bus interface or AXI/AHB dual-bus interface with configurable data width;
· Supports single precision and double precision data types;
· Supports big endian and little endian modes;
· Supports on-chip hardware debugger;
Main technical parameters of CK807
CK807’s application fields
· HDTV and STB (set top box);
· High-end audio & video applications;
· High-end control applications;
· High-end SSD controller;
Structural and design features of CK807
CK807 implements an optimized architecture for high-efficiency computing. It adopts 8-stage dual-issue pipeline. Fetch unit is designed with low-cost hybrid branch predictor to support two-level dynamic branch prediction, return address prediction and indirect jump address prediction. Distributed reservation stations is designed to support out-of-order issue and execution of instructions, and Load/store unit adopts in-order, non-blocking execution mechanism. To improve power efficiency, CK807 is designed with access filtering technique for instruction/data cache and low-power execution technique for hot loop programs.
CK807 supports Harvard memory architecture. Single-AXI-bus interface or AXI/AHB dual-bus interface is configurable for users. Multi-beat outstanding access is supported to improve the bus bandwidth.CK807 also supports the management of memory address and realizes the mapping of virtual address to physical address via hardware TLB. Finally, CK807 supports various low-power operating modes and fine-grained clock gating logic.
CK807 supports multi-core designs to further scale performance increase. CK807MP supports collaborative working of 1~4cores with SCU (Snoop Control Unit) to realize cache coherence. CK807MP also supports different multi-processing architectures including symmetric multi-processing (SMP) and asymmetric multi-processing (AMP). CK807MP fully supports mainstream SMP operating systems.
Floating point arithmetic unit of CK807
CK807 is designed with configurable IEEE-754 compliant floating-point units. It supports single-precision, double-precision and SIMD floating-point processing. To ensure better energy efficiency, optimizing execution delay of pipeline and hardware resource reusing are implemented in CK807 FPU.